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Altera_Forum's avatar
Altera_Forum
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8 years ago

Strange comparator behavior

I have a simple comparator project which compares two 2-bit words. I wrote a code, but time diagrams show some strange behavior: library IEEE; use IEEE.std_logic_1164.all; entity cmp is port ( x...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

There are also issues with your code.

You are using std_logic inputs, and using > to compare them. in VHDL, std_logic is a 9 state type, with ('U', 'X'. '0', '1', 'Z', 'W', 'L', 'H', '-') as all the states. In simulation, using > may lead to some odd situations as 'Z' and '-' are bother greater than '1'. In real hardware, only '0' and '1' can exist (and 'Z' on a tri state, but it cannot be checked for on hardware).

So, I recomend using only = when comparing std_logic