Honored Contributor
Honored ContributorThis is not a bug. This is your circuit using logic clocks.
Like I said, user generated clocks are affected by compilation - sometimes you'll get lucky and the routing works, sometimes you wont and the delay is too much. This is why you must use clock enables - they garantee that all signals arrive at the correct time and you'll never get differences between compiles. HDL or schematic does not affect the RTL diagram (look at the RTL schamtic - tools -> netlist viewers -> RTL view). It will be the fitter changing the routing between compiles. The fitter seed is affected by the source. If the source changes even slightly, all the routing will be different. I highly suggest you learn HDL. Schematic pros: - You get a schematic (this is only a pro if you like them) Schamtic cons: - You cant do diffs on them in a version control tool to see whats changed between versions - You cant simulate them directly - Not portable to other non-quartus tools
