Strange bus failure

HDL has some advantages, but Schematic is not without advantages itself. The main advantage is that I can draw a schematic, but I don't yet understand how to write HDL code (although I can read it a little bit).

I don't understand what you mean by substituting clock enables for actual clocks. The design needs clocks at a particular frequency - especially the baud clock. The uart synchronously clocks off that and not the 48Mhz. It simply wouldn't be practical to try to make it work at 48MHz.

However, it is possible that the problem I am experiencing is the baud rate generator failing rather than the bus. I'm not sure how since its just a big 16 bit counter (synchronous to 48 MHz).

I drew up an 8 digit frequency counter that I can use to test the output of the baud rate generator. I'll reinstall the stock Altera HDL 74163 and see if the problem returns. The HDL is most likely altering the routing, but it shouldn't cause the routing to silently fail (there were no compile errors).

I'll post my results later.