Strange bus failure

HDL and schematics mix just fine, and it is highly recomended that you do all of your design in HDL (because it is easier to store in a revision control, easier to simulate, more portable etc).

The problems in the design are probably much to do with the logic generated clocks. Creating clocks with logic (even slow ones) is not recomended. You can get all sorts of problems because they are highly affected by routing, tempurature, voltage and they are not checked by timing analysis.

You need to use the same 48MHz clock for the whole system, and generate clock enables instead of actual clocks.