Strange bus failure

I wanted to clean up the project a bit before posting and there was an Altera stock component 74163 that was written in HDL. Since I wanted my project to be in all schematic, I replaced their 74163 with one that I drew up myself.

The problem is that doing that seems to have fixed the bus problem at the top level. The Altera HDL 74163 was several levels down and had nothing to do with the receiver circuit. The receiver circuit already had the new 74163 circuits.

Anyhow, I'm not sure just how much debugging is going to be possible since its working now, but I would like to know what is causing this.

Could the compiler be upset when schematic and HDL are mixed? Perhaps a bug where they don't get along?