Forum Discussion
Altera_Forum
Honored Contributor
9 years agoYes, you can connect the SDRAM Controller Core IP directly to your VHDL. Generate the rtl through Qsys and instantiate it, using the generated module template, in your VHDL.
Cheers, AlexYes, you can connect the SDRAM Controller Core IP directly to your VHDL. Generate the rtl through Qsys and instantiate it, using the generated module template, in your VHDL.
Cheers, Alex