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changdou013
New Contributor
New ContributorStitching user logic to M-series NoC
I am trying to stitch user logic to the M-series NoC example design[DDR]. Platform Designer validates the design and the design passes analysis and elaboration stage however fails in synthesis stage due to : Missing NoC assignments. Even though the assignments have been done in NoC assignment editor. Is this a known issue or am I doing something wrong?
1 Reply
sstrellSuper Contributor
Can you provide the full error message? Did validation pass in the NoC Assignment Editor? What do your assignments in the NoC Assignment Editor look like?
