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Altera_Forum
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13 years ago

std_logic_vector VS unsigned

I have the following type definitions subtype msgBlock_t is std_logic_vector((Z-1) downto 0); subtype msgBlock_u_t is unsigned((Z-1) downto 0); type msgBlocks_t is array((K_B-1) dow...
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Altera_Forum
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13 years ago

there is nothing wrong with unsigned for memories and registers. I avoid std_logic_vector whenever another type is more appropriate.

You havent shown the definition of out_xor_L1.