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Altera_Forum's avatar
Altera_Forum
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12 years ago

State Machine register "alias"

Hi,

I have a state machine which I have defined as: 

enum bit  {S_WAIT = 2'b01, S_DOSTUFF = 2'b10} dumb_state, dumb_next_state;

After compiling this correctly gets detected as a state machine by Quartus.

I also have status register that I can access via a AvMM bus defined as: 

logic  status_reg;

I want to read the state value via my status register for debug purposes. So I did the following assignment: 


always_ff @(posedge clk) begin
    status_reg <= dumb_state;
end

This compiles fine as well. However, now Quartus is not detecting my state machine. I'm guessing this is happening because dumb_state is being analyzed as a standard logic element due to the assignment made. Is there any way to get around this?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I forgot to mention that using a case statement does work... I just think that that isn't an elegant solution especially when there are a lot of states. 

    
always_ff @(posedge clk) begin
    case (dumb_state) 
        S_WAIT: status_reg <= 2'b01;
        S_DOSTUFF: status_reg <= 2'b10;
    endcase
end
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Recognizing state machines allows optimizations such as dead state removal and optimal encoding (FPGA usually use one hot encoding).

    However, by exposing the state via status_reg, you're forcing the encoding to be your own and thus disabling those optimizations.

    That's why Quartus won't recognize it.

    Maybe with the use of SystemVerilog casting you can get it as you wish:

    status_reg <= int'(dumb_state); // or something like that

    But this might be a terrible idea anyway, as you'll end up with logic to translate from the encoding Quartus is actually using to the encoding you've specified for status_reg.

    All in all, I would go with the original code you have and not spend much time chasing other solution.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I had tried casting and it didn't help.

    A slightly less verbose method I came up with was to do something like this: 

    status_reg <= {(dumb_state == S_DOSTUFF), (dumb_state == S_WAIT)};

    It synthesized exactly the same way as the case statement method.