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Altera_Forum's avatar
Altera_Forum
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12 years ago

State Machine register "alias"

Hi, I have a state machine which I have defined as: enum bit {S_WAIT = 2'b01, S_DOSTUFF = 2'b10} dumb_state, dumb_next_state; After compiling this correctly gets detected as a st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I forgot to mention that using a case statement does work... I just think that that isn't an elegant solution especially when there are a lot of states. 


always_ff @(posedge clk) begin
    case (dumb_state) 
        S_WAIT: status_reg <= 2'b01;
        S_DOSTUFF: status_reg <= 2'b10;
    endcase
end