state machine problem

I create a vhdl program that is a state machine, it compile, but in the vector waveform i cant see my actual state (pr_state) and my next state (nx_state), i dont know what to do, please i need help :(

this is the vhdl code:

Library ieee;

use ieee.std_logic_1164.all;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

---------------------------------------

ENTITY maquinaest IS

PORT ( clock,reset:in STD_LOGIC;

S:STD_LOGIC_VECTOR(1 DOWNTO 0);

v: out STD_LOGIC);

END maquinaest;

---------------------------------------

ARCHITECTURE secuencial of maquinaest IS

type state is (e_0, e_1);

signal pr_state: state;

signal nx_state: state;

BEGIN

---------------LOWER SECTION:--------------------------

PROCESS(reset, clock)

BEGIN

IF(reset='1')THEN

pr_state<=e_0;

ELSIF(clock'EVENT AND clock='1') THEN

pr_state<=e_1;

END IF;

END PROCESS;

---------------UPPER SECTION:--------------------------

PROCESS(S,pr_state)

BEGIN

CASE pr_state IS

WHEN e_0 =>

IF(S="00")THEN

v<='1';

nx_state<=e_1;

END IF;

IF(S="01")THEN

v<='0';

nx_state<=e_0;

END IF;

IF(S="11")THEN

v<='0';

nx_state<=e_0;

END IF;

WHEN e_1 =>

IF(S="11")THEN

v<='0';

nx_state<=e_0;

END IF;

IF(S="01")THEN

v<='1';

nx_state<=e_1;

END IF;

IF(S="00")THEN

v<='1';

nx_state<=e_1;

END IF;

END CASE;

END PROCESS;

END secuencial;