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Altera_Forum's avatar
Altera_Forum
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15 years ago

state machine problem

I create a vhdl program that is a state machine, it compile, but in the vector waveform i cant see my actual state (pr_state) and my next state (nx_state), i dont know what to do, please i need help ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

this should not be the problem. Just edit your waveform file as you did for the simulation you ran:

- delete both nodes pr_state and nx_state

- insert node => select only pr_state and nx_state (no "not state type" nodes)

- this should change the "Type" to Machine and "Value Type" to "Enum"

- insert the node(s) and your next simulation should show the states...

Hope that helps,

Carlhermann