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Altera_Forum's avatar
Altera_Forum
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15 years ago

state machine problem

I create a vhdl program that is a state machine, it compile, but in the vector waveform i cant see my actual state (pr_state) and my next state (nx_state), i dont know what to do, please i need help ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I think the problem is, that in the "LOWER SECTION" you assign either e_0 to pr_state or (for no reset condition) permanently e_1. The output "v" is based on pr_state and while assigning different values to nx_state in the Upper Section, this change of "nx_State" has no effect on pr_State. Therefore the compiler optimizes an may reduce your state machine to some "simple registered logic"...

In short words: I think the failure is located in the lower section, the assignment for the "non reset" path should write

ELSIF(clock'EVENT AND clock='1') THEN

pr_state<=nx_state;

Give it a try...

Carlhermann