state machine not holding variable value outside state

I beg to differ: there is nothing wrong using the 2-process state machine approach nor with using variables. You just have to be careful.

The 2-process state machine, maybe be old but certainly not out of fashion. It allows you to generate both combinatorial and synchronous outputs. If you use the 1-process synchronous approach and you need combinatorial outputs, e.g. a master state machine controlling a number of slave state machines or stimulating an external device, you still have to create a second combinatorial process where you have to decode the same conditions as in the synchronous process. I do agree that we may not need combinatorial signals that often.

Variables, local to the process, are fine but you must of course be fully aware of the behaviour of a variable in VHDL. You could compare it to the variable in a C function, which doesn't hold its value between calls. If that is necessary you have to use either a global variable (a signal in VHDL) or the 'static' attribute (no matching VHDL construct) to preserve the value until the next call. In VHDL a process is activated for every change in the sensitivity list, which is kind of analogous to calling a C-function. If you need persistence e.g. a counter you cannot use a variable but resort to a signal (declared outside the process).