state machine file

i create a state machine using the state machine file (.smf) or editor, but i have a problem i have two states, but quartuss II doesnt acept more than one transition to the same state, and in my design i have two transition to the same state(state1) , and one transition to to the other state (state2), and the same in state2, two transitions to state 2 and one transition to state1.

I need help, this is the vhdl that generated the programm and also this is the diagram.

-- Copyright (C) 1991-2009 Altera Corporation

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-- Agreement, or other applicable license agreement, including,

-- without limitation, that your use is for the sole purpose of

-- programming logic devices manufactured by Altera and sold by

-- Altera or its authorized distributors. Please refer to the

-- applicable agreement for further details.

-- Generated by Quartus II Version 9.1 Build 222 10/21/2009 SJ Full Version

-- Created on Tue Apr 27 18:06:02 2010

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY states IS

PORT (

clock : IN STD_LOGIC;

reset : IN STD_LOGIC := '0';

sa : IN STD_LOGIC := '0';

sb : IN STD_LOGIC := '0';

v : OUT STD_LOGIC

);

END states;

ARCHITECTURE BEHAVIOR OF states IS

TYPE type_fstate IS (state1,state2);

SIGNAL fstate : type_fstate;

SIGNAL reg_fstate : type_fstate;

SIGNAL reg_v : STD_LOGIC := '0';

BEGIN

PROCESS (clock,reg_fstate,reg_v)

BEGIN

IF (clock='1' AND clock'event) THEN

fstate <= reg_fstate;

v <= reg_v;

END IF;

END PROCESS;

PROCESS (fstate,reset,sa,sb)

BEGIN

IF (reset='1') THEN

reg_fstate <= state1;

reg_v <= '0';

ELSE

reg_v <= '0';

CASE fstate IS

WHEN state1 =>

IF ((NOT((sa = '1')) AND NOT((sb = '1')))) THEN

reg_fstate <= state2;

ELSIF ((NOT((sa = '1')) AND (sb = '1'))) THEN

reg_fstate <= state1;

-- Inserting 'else' block to prevent latch inference

ELSE

reg_fstate <= state1;

END IF;

IF ((NOT((sa = '1')) AND NOT((sb = '1')))) THEN

reg_v <= '1';

-- Inserting 'else' block to prevent latch inference

ELSE

reg_v <= '0';

END IF;

WHEN state2 =>

IF (((sa = '1') AND (sb = '1'))) THEN

reg_fstate <= state1;

ELSIF ((NOT((sa = '1')) AND (sb = '1'))) THEN

reg_fstate <= state2;

-- Inserting 'else' block to prevent latch inference

ELSE

reg_fstate <= state2;

END IF;

IF ((NOT((sa = '1')) AND (sb = '1'))) THEN

reg_v <= '1';

-- Inserting 'else' block to prevent latch inference

ELSE

reg_v <= '0';

END IF;

WHEN OTHERS =>

reg_v <= 'X';

report "Reach undefined state";

END CASE;

END IF;

END PROCESS;

END BEHAVIOR;