State machine counter problems

There are several things wrong here:

1. Because of the way VHDL works, your outputs will only change when Ain, Bin or present_state actually change. Be warned - the way you have your circuit will mean that the code will behave differently to hardware.

2. How would you expect the counters to work. Your code implies that the counters should add one when conditions are met - but they will keep adding 1 in a feedback loop. You need to move the counters to a clocked process to actually work as expected.