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Altera_Forum's avatar
Altera_Forum
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12 years ago

standard deviation and covarience VHDL implementation

hi

i've built a component that calculates standard deviation & covariance

hence i 've used real(), to_stdlogicvector(), integer(), to_integer() and a converting methods to satisfy the 2 equations for std dev and cov.

i've just knew that this could be synthesized as real() is not synthesized, and i think that the other mentioned methods are not synthesized too...

any idea how can i make my code synthesized or what to replace these methods with..

thanks,

Niveen..

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Do you actually need reals? If possible it is a lot easier and more efficient to use integer arithmetic. In that case you can just use ieee.numeric_std.all and its unsigned and signed types.

    If you absolutely need to use reals, I suggest to have a look at Altera's floating points megafunctions.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    to_stdlogicvector() is non standard, and it's recommended not to use it. Instead use the signed and unsigned types from numeric_std, and the to_unsigned() and to_signed() functions. Those are synthesizable (from integer), as is to_integer() (from unsigned and signed).