SRAM IP that work on some builds, and some it doesn't!

No, you got that reverse.

You're telling the fitter it has 9.35 of maximum external delay, so in this case it will try to keep the internal FPGA delays it under 10.65 ns.

Note that with aSRAM, the write sequence generaly needs to ensure you setup valid address and data a bit before you activate the write enable and you hold those valid address and data for a bit after you've disabled the write enable.

Otherwise, you risk writing random stuff into random addresses.

You need a small state machine to ensure that...