SRAM IP that work on some builds, and some it doesn't!

Thanks Ted,

I've fixed the ( CS == 0 ) issue. :-)

I'm hoping to fix this in TimeQuest with constraints. I've added below to my sdc, to account for SRAM time to clock out (tCO) and board delay (BDa):

set_output_delay -add_delay -clock "clk_50" -max [expr $local_osc_period - $SRAM_tCO_max - $SRAM_BDa_max] [get_ports {sram_*}]

Where

[LIST]

local_osc_period = 20

SRAM_tCO_max = 10.5

SRAM_BDa = 0.15

[/LIST]

My understanding is that this would ensure the fitter places the design so the propagation delay from FPGA -> Pin is less than 20-10.5-.15 = 9.35ns. That way I can keep the memory single cycle access; I don't want latency, so don't want to over-register everything. It works right now, but I'm going to need to test and look closer to ensure it's a solution, not just luck of the fitter.

Can you advise what other constraints I should add?