SRAM IP that work on some builds, and some it doesn't!

Thanks DSL,

I've tried that, with this code, which has the same behaviour:

module sram
(
	//	global clk/reset
	input wire 		clk,
	input wire 		reset_n,
	// avalon slave
	input wire									s_chipselect_n,
	input wire 		 	s_byteenable_n,
	input wire									s_write_n,
	input wire 									s_read_n,
	input wire		 	s_address,
	input wire		 	s_writedata,
	output wire 	 	s_readdata,
	
	// SRAM interface
	inout wire		 	SRAM_DQ,
	output reg		 	SRAM_ADDR,
	output reg 		SRAM_UB_n,
	output reg 		SRAM_LB_n,
	output reg 		SRAM_WE_n,
	output reg 		SRAM_CE_n,
	output reg 		SRAM_OE_n
);
	parameter DATA_BITS		= 16;
	parameter ADDR_BITS		= 18;
	// internal registers
	reg writedata_reg;
	// combinatorial outputs
	assign	SRAM_DQ 			=	SRAM_WE_n ? 'hz : writedata_reg;
	assign	s_readdata			=	SRAM_DQ;
	
	// synchronous registers
	always @ ( posedge clk )
	begin
		if ( s_chipselect_n == 0 ) // if this component selected
		begin
			writedata_reg 				<= s_writedata; 	// register the write data	off the bus		
			SRAM_ADDR				<=	s_address;		// clock through other outputs to sram
			SRAM_WE_n				<=	s_write_n;
			SRAM_OE_n					<=	s_read_n;
			SRAM_CE_n					<=	s_chipselect_n;
			{ SRAM_UB_n,SRAM_LB_n }		<=	s_byteenable_n;
		end
	end
endmodule

What SignalTap is tell me, is that there is no chip select, no write and no read signal. So the bus is trying to read from the SRAM address space, but the control signals are not being asserted... In Nios I'm looping a memory test over the SRAM space. Could this be a problem on the avalon bus side of things? Is my code being optimised out for some reason?