SRAM IP that work on some builds, and some it doesn't!

The write enable signal (from the Avalon faric) is only valid on the relevant clock edge (and probably qualified by some other signals).

It could quite possibly be asserted (for short times) at any other time - which will generate random writes to your SRAM.

So while you can do completely async reads, you have to synchronise the writes to the avalon clock.