SRAM IP that work on some builds, and some it doesn't!

Thanks Guys,

To take care of the timing sequences, do i just need to constrain the device IO in an SDC file? Is that the best way to go about it?

My understanding was that the aSRAM would latch the data out upon presentation of WE_n, CS_n and ADDR. The timing of this device is 4.5ns setup for a read, with 0ns hold requirement. The avalon bus would then sample the DATA on clock rising, job done...