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anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago
Solved

Splitting bidirectional vector into bits

Hi, As the title suggests, I'm trying to split the bidirectional vector into single bidirectional bits for my design. I have a dedicated IP (which I can't modify) and that one has a bit vector of ty...
Hdl
  • FvM's avatar
    FvM
    2 years ago
    Hi
    you can't assign an inout port to a signal, but you can directly assign it in the component instantiation.
    e.g.
    generic_quad_spi_controller2_0_qspi_pins_data(0) => QSPI_IO1,
    2_0_qspi_pins_data(1) => QSPI_IO2,
    etc.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
Hi
you can't assign an inout port to a signal, but you can directly assign it in the component instantiation.
e.g.
generic_quad_spi_controller2_0_qspi_pins_data(0) => QSPI_IO1,
2_0_qspi_pins_data(1) => QSPI_IO2,
etc.
  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Or use a concatenation on the right side
    generic_quad_spi_controller2_0_qspi_pins_data => QSPI_IO4 & QSPI_IO3 & QSPI_IO2 & QSPI_IO1,
    • anonimcs's avatar
      anonimcs
      Icon for Contributor rankContributor
      2 years ago

      I remember getting some errors before due to concatenating 2 signals (or a fixed value + a signal) at the component instantiation but they both look promising, thanks!