Splitting bidirectional vector into bits

Hi,

As the title suggests, I'm trying to split the bidirectional vector into single bidirectional bits for my design. I have a dedicated IP (which I can't modify) and that one has a bit vector of type inout for Quad SPI (the data for QuadSPI). And I want to communicate with a NOR Flash, but since Quad SPI has 4 data lanes, I wanted to split the inout vector coming from the IP and then assign my top level ports with those bits separately.

Do you know what's the most convenient way of doing it ? I tried adding two processes (given below) but I got the error " QSPI_IO1 directly or indirectly feeds itself". (and ofc the same for the other 3 data ports)

Thanks in advance !

entity myEntity is
	port
	(
		CLK 			: in  std_logic;
		QSPI_CLK		: out   std_logic;
		QSPI_CSN		: out   std_logic;
		QSPI_IO1		: inout std_logic;
		QSPI_IO2		: inout std_logic;
		QSPI_IO3		: inout std_logic;
		QSPI_IO4		: inout std_logic;
	);
end myEntity;

architecture rtl of myEntity is
	signal qspi_data_vector : std_logic_vector(3 downto 0); -- 4-bit std_logic_vector

component tx_soc is
		port (
			clk_clk                                            : in  std_logic                     := 'X';              -- clk
			reset_reset_n                                      : in  std_logic                     := 'X';              -- reset_n
			generic_quad_spi_controller2_0_qspi_pins_dclk      : out std_logic;                                         -- qspi sclk
			generic_quad_spi_controller2_0_qspi_pins_ncs       : out std_logic;                                         -- qspi ss_n
			generic_quad_spi_controller2_0_qspi_pins_data      : inout std_logic_vector(3 downto 0) := (others => 'X'); -- qspi data
		);
	end component tx_soc;
p_qspi_data_merge: process (QSPI_IO4, QSPI_IO3, QSPI_IO2, QSPI_IO1)
	begin
		-- Concatenate the QSPI port signals into qspi vector
		qspi_data_vector <= QSPI_IO4 & QSPI_IO3 & QSPI_IO2 & QSPI_IO1;
	end process;

	p_qspi_data_split: process (qspi_data_vector)
	begin
		-- Split the concatenated the QSPI port signals into single bits
		QSPI_IO1 <= qspi_data_vector(0);
		QSPI_IO2 <= qspi_data_vector(1);
		QSPI_IO3 <= qspi_data_vector(2);
		QSPI_IO4 <= qspi_data_vector(3);
	end process;

soc_inst : component tx_soc
	port map (
		clk_clk                             => core_clk,
		reset_reset_n                       => nios_reset_n,
		--
		generic_quad_spi_controller2_0_qspi_pins_dclk    => QSPI_CLK,
		generic_quad_spi_controller2_0_qspi_pins_ncs     => QSPI_CSN,
		generic_quad_spi_controller2_0_qspi_pins_data    => qspi_data_vector
	);

end;