Split BUS into 2 sub-BUS'es - How to do in QII Schematic entry?

So I read multiple posts about splitting BUS in QII but all these are describing example where bus is split into individual signals.

Very helpful, but I have different problem.

I have 16-bit counter with outputs as bus

q[15..0].

these outputs must be connected to two individual ram blocks address lines,

one memory block has 5-bit address, another has 10-bit address:

m1[4..0]

m2[10..0]

how can I assign:

q[15..11] to connect with m1[4..0]

and

q[10..0] to connect with m2[10..0]

? Thanks in advance.

:confused:

p.s. I also appreciate help in similar but more advanced example when splitting same counter output bus [15..0]

and assigning to 8-bit addressable memory blocks as follow:

q[15..11, 2..0] to connect with m1[7..0]

and

q[10..3] to connect with m2[7..0]

?