Altera_Forum
Honored Contributor
Honored ContributorSPI Slave Implementation
I am writing a code of SPI slave in FPGA. Is it necessary to sync my FPGA global clock and serial clock ? If so can someone tell me the pros & cons for the same ?
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have some another question! Is it necessary to use CS(Chip Select) signal in SPI ? If I am using only one slave then can I connect this CS pin to ground permanently ? --- Quote End --- No, generally you should use a chip select. Why? Because the SPI device uses chip-select to determine the start of a transaction. For example, lets say your FPGA is the SPI master communicating with some SPI slave. What happens to the SPI clock during power on? As the FPGA turns on, if weak pull-ups are enabled, there will be a rising-edge, and then perhaps your SPI clock is reset low (i.e., the FPGA configured state drives SPI clock low). Does the SPI device consider this a single clock? Who knows? You should read the data sheet for your device. Use the SPI chip select and things will just work correctly. Cheers, Dave
