SPI Slave Implementation

--- Quote Start ---

Is it necessary to sync my FPGA global clock and serial clock?

--- Quote End ---

It depends on your hardware implementation. Here's two implementation options;

1. Use the SPI clock to serialize and deserialize bytes, and then use clock-domain crossing logic to send the bytes to the FPGA clock domain. This is how the SPI-to-Avalon bridge works.

2. Use the FPGA clock to "synchronize" (dual-DFF) the SPI clock, and then use an edge-detect (DFF delay and combinatorial logic) the pulses for rising-edge and falling-edge. Use an FSM in the FPGA clock domain to determine when to clock data in, or out.

I've used both techniques before. When using (1), you have to make sure your clock is clean, i.e., no ringing on the edges.

If your FPGA clock is much faster than your SPI clock, then I'd recommend using (2). If they are comparable, then (2) will not work, so you'd have to investigate using (1). If your FPGA has a PLL, then you could try both techniques.

Cheers,

Dave