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tnehowig's avatar
tnehowig
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SPI (3-Wire Serial) Intel FPGA IP sending 16 bits for every byte write

Hello, I'm having an issue with the SPI port sending out 16 clock cycles every time I try and write a single byte using a NIOS2f. I've verified that the Data Register Width is set to 8 in Platfo...
  • SyafieqS's avatar
    SyafieqS
    5 years ago

    Hi Tyler,

    Glad you had solved the issue. Most of the time, it is always recommended to regenerate you IPs. The feature you said if you turn it on, it will automatically generates IP before compiling the design as it indirectly terminates the manual way where you generate in PD --> add new .qip --> and recompile.

    Thanks,

    Regards

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Tyler,

Glad you had solved the issue. Most of the time, it is always recommended to regenerate you IPs. The feature you said if you turn it on, it will automatically generates IP before compiling the design as it indirectly terminates the manual way where you generate in PD --> add new .qip --> and recompile.

Thanks,

Regards