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Altera_Forum's avatar
Altera_Forum
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12 years ago

speed of execution of a design with eliminated latches

This is partly from a previous thread "converted to equivalent circuits with latches". As shown below: always @(posedge clk or posedge reset) begin if(reset) begin: OVER_LOOP // totally 8 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Again, is there a way I could do the reset for the initial values, and at the same time, do the calculation for the next round of 8 iterations in one clock cycle? I try to put if...if there, so that the two if blocks could be done sequentially in one clock cycle, but Verilog doesn't allow me to do so.

Thanks for any ideas to solve the problem in advance!