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set_false_path -from *|TD_low_phase_reg -fall_to TXC
set_false_path -from *|TD_high_phase_reg -rise_to TXC
Naturally, for this to be safe, the registers must not fan-out to any other TXC-clocked destinations.
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You can use virtual clocks for the -clock argument in input delay and output delay constraints. A virtual clock can let you be more precise with false-path exceptions (like Tristan's) or multicycle exceptions for I/O paths. Also, the same port (device pin) can have input/output-delay constraints for more than one virtual clock, allowing the same port to have more than one I/O timing constraint for more than one register (like an output enable register and a data register feeding the same device pin).
In an earlier post, Tristan had this clock:
create_clock -name TXC -period 8 [get_ports TXC]
For a virtual clock, simply omit the target:
create_clock -name TXC_virtual_just_for_io_use -period 8
Then use the virtual clock in the output-delay constraint and in the false-path exception:
set_false_path -from *|TD_low_phase_reg[*] -fall_to TXC_virtual_just_for_io_use
A virtual clock can also let you use clock-to-clock exceptions instead of path-based exceptions for more efficient exception processing by TimeQuest. For example:
set_false_path -from TXC -fall_to TXC_virtual_just_for_io_use
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