Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Specifying the latch edge for DDR output timing

This is a problem that I've had hanging over me for a while. I'm hoping someone can shed light on it. So, I need to implement some DDR output logic (not for memory, but just to send a high-spee...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Our target is a Cyclone II C7.

I actually just thought of the extra stage approach too and tried it earlier today. You're right--It pretty much eliminates the problem. I can live with that solution. There might be glitches on the output bus due to switching the mux and register at the same time, but that's not something I'll lose sleep over.

Thanks for the help!