Specifying the latch edge for DDR output timing

I did a DDR I/O design with time quest some months ago and will again soon at a faster clock rate. So I would like to spend some time this afternoon to reproduce your question in quartus and get an understanding of the requriement and develop for both of us the best answer. I'll build a test case in VHDL unless you already have a code snippet or bdf you want me to use.