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Altera_Forum
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10 years ago

Source synchronous transmitter constraints

Hi all, before I start, I have read the Altera doc on this many times and often seem to end up confused one way or another though I have successfully constrained such interfaces before now. T...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Hello,

Should not you be using create_generated_clock in following way?

create_generated_clock -name TX_CLK -source {surface_card_0|pll_tx_clk|altpll_component|auto_g enerated|pll1|clk[0]} [get_pins {div|q}] -divide_by 4

where instead of DIV you should mention your register name.

Reference : https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf ( Figure 3, Example 3 )

Please share your view as I am also facing problem in giving constraints.

Regards,

Bhaumik