Contributor
Regular ContributorHi,
From the design, the DATAINHI and DATAINLO are connected to 1'h1 and 1'h0.
In general, you would see clock sources as the starting point of timing paths in a "clock-as-data" scenario, when a clock feeds a data input pin of a register (or an output pin with a "data-like" constraint like set_output_delay).
Looking at the circuit in netlist viewer, it seems that the PLL output is driving "CLKHI", "CLKLO" and "MUXSEL" inputs of the DDIO_OUT blocks. Looking at the timing path report (pasted below), it looks like the MUXSEL input is modeled as a data input (as opposed to a clock input). So, we have a "clock-as-data" path, where the PLL output clock is driving the ssync_tx_data pin (via MUXSEL of the DDIO), which has a set_output_delay constraint, creating a valid timing path.
So, Timing Analyzer behavior looks correct.
The clock is 0ns from input pins, get shifted by 2ns through the PLL . This clock inst8|pll_1_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk has 2ns delay compared to inst8|pll_1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk, which is why the latch clock edge is 2ns but not 0ns.
Thanks.
ContributorHi YY.
Thank you very much for your answer.
I suppose I need to summarise the case. I think that our discussion could be at that point helpful for the community.
First of all, I again can repeat - "as for the data path, there are no constant values on DATAINHI and DATAINLO". But yes, DATAINHI and DATAINLO are indeed connected to 1'h1 and 1'h0, but it's NOT a data path,
it's a clock path, and it's excluded from the timing with set_false_path constraint, as I mentioned earlier. So there is no need to think about it and this has nothing to do with the case.
As about your further explanation, thank you very much, it's like I explained it in my post here, so you confirmed my guess with a detailed explanation!
But final problem - I'm still observe I can't describe my problem properly because what you wrote is obvious-
again, my question is - Why in the detailed timing report the phase shift of clock (2 ns) is introduced at the beginning (from the input port), not after it enters PLL and gets shifted inside of it.
I understand and yes, you are right, latch edge of course is 2 ns, it's because of the shift, but in DETAILED timing report we observe path from the input pin, and the shift should be in that case INSIDE the PLL,
not on the pin.
Thank you very much again.
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Best regards,
Ivan
