Source Synchronous representation in TimeQuest - FPGA is a transmitter

Hi sstrell.

Yes, my .sdc file looks like that:

create_clock -period 8.0 -name fpga_clk [get_ports fpga_clk]

# Constrains PLL outputs. One output has 90 degree phase-shift for transmit clock

derive_pll_clocks

derive_clock_uncertainty

# Put a generated clock on output clock port to be referenced by set_output_delay constraints

create_generated_clock -source [get_pins {inst8|pll_1_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -name ssync_tx_clk_ext [get_ports {ssync_tx_clk}]

set_output_delay -clock ssync_tx_clk_ext -max 0.9 [get_ports {ssync_tx_data[*]}]

set_output_delay -clock ssync_tx_clk_ext -min -1.0 [get_ports {ssync_tx_data[*]}]

set_output_delay -clock ssync_tx_clk_ext -max 0.9 [get_ports {ssync_tx_data[*]}] -clock_fall -add_delay

set_output_delay -clock ssync_tx_clk_ext -min -1.0 [get_ports {ssync_tx_data[*]}] -clock_fall -add_delay

set_false_path -fall_from [get_clocks {inst8|pll_1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks ssync_tx_clk_ext] -setup

set_false_path -rise_from [get_clocks {inst8|pll_1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks ssync_tx_clk_ext] -setup

set_false_path -fall_from [get_clocks {inst8|pll_1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks ssync_tx_clk_ext] -hold

set_false_path -rise_from [get_clocks {inst8|pll_1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks ssync_tx_clk_ext] -hold

set_false_path -to [get_ports {ssync_tx_clk}]

So I can confirm that my constraints are like you suggested.

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Best regards,

Ivan