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Altera_Forum
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15 years ago

Source-synchronous constraints with the -reference_pin option

Hello All, I have a Cyclone III with a large number of source-synchronous inputs and outputs that need to be constrained in the SDC file. I have tried to constrain then using the -reference_pin...
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Altera_Forum
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15 years ago

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As for thew -reference_pin option, I have never used it. What I would do is to create a generated clock for the output clock.

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Do both methods give the exact same result?

According to this page (http://www.altera.com/support/examples/timequest/exm-tq-basic-source-sync.html) on the Altera website, "The -reference_pin option automatically includes the clock latencies to the specified port or pin." Does the create_generated_clock method achieve this as well?

Timing constraints is the aspect about FPGA development that I feel the least confident about.