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Altera_Forum's avatar
Altera_Forum
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15 years ago

Source synchronous constraints for both edges in TimeQuest

I've been working my way through the tutorials and Rysc's document. Unfortunately, the waveforms don't match what I'd expect. I thought I'd see the min-rise output delays from the rising edge of th...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The issue of hold false paths as you last put is correct.

I am not sure about your case as there are exceptions depending on the case. Here are some points to check:

(1) whether your case is same edge launch/latch or opposite edge launch/latch. This depends on your interface design.

(2) whether data is edge aligned (zero delay without PLL or with PLL set to zero). Or that it is not edge aligned (termed centre aligned)

(3) you will need to apply exceptions to inputs and outputs

(4) you will need to set delay values as required by external delays and device.

You will see examples in the doc AN 433: Constraining and Analyzing

Source-Synchronous Interfaces