Source Synchronous Analysis with TimeQuest

So for something like Stratix IV/V, there are dedicated LVDS serializers in the I/O, along with a dedicated clock tree to drive them. Basically the entire receiver is in hard logic and there is no variability. When used, these run much faster than just putting down a PLL and two DDR input registers. Part of the reason is because they are made from this dedicated silicon, and part is because they can be timing analyzed as a macro, and all the pessimisms/unknowns can be removed. In fact, the timing analysis is significantly different. If you build two DDR registers, you have to do timing constraints like my guide shows, but if you use the dedicated silicon via the altlvds_rx megafunction, TimeQuest will spit out an RSKM number and you should use that(and it will be a very good number.) (Also note that altlvds_rx with a deserialization factor of 2 will build the circuit with DDR registers and the timing analysis I've described, so it's not a given that using altlvds_rx will use the dedicated silicon).

Because of the dedicated deserializers and what not, those devices have data sheet values of how fast they can run. They look a lot like this Cyclone IV data sheet number. Yet I threw down an altlvds_rx into that design(make the deserialization a factor of 4) and tried to run it at 350MHz/700Mbps, but it did the regular timing analysis(no RSKM) and failed.

Please file an SR on how to do that or what they mean. Please update this post with your results, as I should know this too. (It sounds like it doesn't help, but all the V series, including Cyclone V, have the dedicated serdes logic for LVDS, enabling much higher data rates, and somewhat making my app note less relevant.