Source Latency Definition

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But jump now to the first case of confusion for me, namely the description of the set_input_delay command option -reference_pin <target>. Here the text reads:

specifies a pin or port in the design from which to determine source and network

latencies. this is useful to specify input delays relative to an output port fed by a

clock.

Can someone help me to translate that excerpt? How can one even conceive of input delays relative to an output port? What does that mean?

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It is confusing as such but could it be context related i.e. applies to the case when clock is output from fpga to get data from a device(clk opposite data direction).

Your thoughts about external delay/internal delay are correct. I don't see why altera technical editor has changed names to source/network delay.

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Another source of confusion on this subject is found just below the description of the create_generated_clock command. The text reads:

source latencies are based on clock network delays from the master clock (not

necessarily the master pin). you can use the set_clock_latency -source

command to override source latency.

Based on clock network delays? That is confusing because "source" and "network" delays are seemingly independent based on the definition I cited earlier in this post. I thought source delays were external to the device. I have been groping with this for too long. Any hints?

Many thanks!

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Possibly, now the technical editor is confused and defines source as "source" literally not as external delay as he first defined it.

The best think to stick to your thoughts of external Vs internal delays.