Altera_Forum
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16 years agoSOPC/NIOS II license issue
Hello there,
I work in a research firm and we have a full version of Quartus II, as well as a number of AMPP/MegaCore options. I would assume that this license is sufficient to compile time-unlimited NIOS II blocks, featuring some Altera basic components (e.g. NIOS II core, EPCS controller, SDRAM controller, UART JTAG, etc.). However, it turns out that the resulting SOF file in my design is time limited (please see the message below). As a result, the EDA netlist writter does not write the VHDL files that I need for a gate-level simulation in Modelsim. Does anyone know if SOPC builder (and/or NIOS II core) require a special license? If yes, please let know which one. I already asked my people here who bought the Quartus II license but they never used SOPC builder before, so they actually don't know. Thanks you. +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* Info: Running Quartus II Assembler Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Tue Oct 20 15:20:41 2009 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off design -c design Info: Writing out detailed assembly data for power analysis Info: Assembler is generating device programming files Info: Design contains a time-limited core -- only a single, time-limited programming file can be generated Warning: Can't convert time-limited SOF into POF, HEX File, TTF, or RBF Info: Quartus II Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 211 megabytes Info: Processing ended: Tue Oct 20 15:20:48 2009 Info: Elapsed time: 00:00:07 Info: Total CPU time (on all processors): 00:00:07 +-----------------------------+ ; EDA Netlist Writer Messages ; +-----------------------------+ Info: ******************************************************************* Info: Running Quartus II EDA Netlist Writer Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Tue Oct 20 15:20:52 2009 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off design -c design Error: Can't generate netlist output files because the file "./design.root_partition.map.atm" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "./design.root_partition.map.atm" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "./design.root_partition.map.atm" is an OpenCore Plus time-limited file Error: Can't generate netlist output files because the file "./design.root_partition.map.atm" is an OpenCore Plus time-limited file Error: Quartus II EDA Netlist Writer was unsuccessful. 4 errors, 0 warnings Error: Peak virtual memory: 183 megabytes Error: Processing ended: Tue Oct 20 15:20:53 2009 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01