Honored ContributorI wrote my own component in Component Editor. After adding into my system the Sopcbuilder assigns the complete address area to my slaves (0x000…-0xfff….), although their actually width is 32 bits large. In the menu of the Comonent Editor the size of the Interface writedata is correct 32 Bit large. It makes no difference if I connect the component to the master-interface or not. What is wrong?
Honored Contributorhow big is your address vector? The sizes of both the address and data vectors are used by SOPC builder to determine the address span of your component.
Honored ContributorMy address vector is 32 big large. Below you can see my interfaces.
avs_s0_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s0_write : IN STD_LOGIC; avs_s0_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s1_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s1_write : IN STD_LOGIC; avs_s1_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s2_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s2_read : IN STD_LOGIC; avs_s2_readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s2_write : IN STD_LOGIC; avs_s2_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s3_address : IN STD_LOGIC_VECTOR (31 DOWNTO 0); avs_s3_write : IN STD_LOGIC; avs_s3_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0); clk : IN STD_LOGIC; rst : IN STD_LOGIC; avm_m1_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); avm_m1_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); avm_m1_write : OUT STD_LOGIC; avm_m1_waitrequest : IN std_logic; avm_m1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)Honored ContributorThat's why it is using all the address space. You should reduce your address vector to the actual size that you require (ex: 3 bits if you have 8 32-bit registers).
The Avalon master should still have a 32-bit address vector though.Honored ContributorThanks a lot. I think that is the problem. I try it :)
