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Altera_Forum's avatar
Altera_Forum
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13 years ago

SOPC to QSYS migration, Increasing number of Logic Cells used

Hi all, I'm trying to migrate an SOPC design to QSYS (using the "direct method" by opening the .sopc file from the QSYS environment), and I'm now bumping into a resource usage problem. ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

no, if you have pipeline stages manually placed in the design then i am not suggesting you remove them. What i am suggesting is that if you want to generate rtl on par with what was generated in sopc builder, you need to (under the project settings tab i believe), change the default of 1 pipeline stage settings to 0 to match sopc builder behaviour.

--dalon