SOPC to QSYS migration, Increasing number of Logic Cells used

Are you saying that the pipelines should be removed from the QSYS design all togheter? Without buffering the read/write accesses it might be difficult to make the design work.

In my design there are several Masters and a slave (NiosII, Deinterlacer, Framebuffer, Framereader) connected an external memory controller (DDR2 SDRAM with ALTMEMPHY). The Deinterlacer uses 5 write/read Masters, and inorder to get the design to work, I placed a pipeline stage between the Deinterlacer and the external memory controller. I'm not sure I can make the design work by removing the pipeline stage.

For the SOPC to QSYS migration, where I recreated the design in QSYS, I'm only using a single reset signal for the entire design, so there are no "accidental" reset signals waiting to happen.

I'll try looking into the SDC constraints again, to see where the timing is failing.

Regards,

Saber890