SOPC Builder "Validation Error"

Can you see any errors on bottom window (just above 'Next', 'Help', etc. buttons) of SOPC Builder when you have selected 'System Content' tab. If there is any error try to fix it first before generating system. It is better if you can provide more details or screen shots!

I too have the same problem. But then there seems to be no other errors when I am try generating the design. I am trying to run the example which is provided by Altera, Tutorial on SOPC builder. The one to simulate the lights....

Try this: Go to the Nios II cpu config and make sure that you set the Reset and Exception vectors. That fixed the problem for me.

you must edit "memory on chip" (if you use it) in the cpu , then you can normal generation

Hello there,

If there are any problems in your SoPC system, they usually show up at the bottom of the screen in the little information window. You must resolve these errors before generating the system.

Hi there jake,

1. You said -
   --- Quote Start ---
   If there are any problems in your SoPC system, they usually show up at the bottom of the screen in the little information window. You must resolve these errors before generating the system.
   --- Quote End ---
   . In this case, it didn't explicitly say anything about the reset and exception vectors, rather just talked about the 'validation errors' so in this case a noob would find it hard to figure out the source.

2. you said -
   --- Quote Start ---
   Not setting the reset and exception vectors for the processor is an error and you cannot generate the system until you've resolved it.
   --- Quote End ---
   . This is obvious in keeping with the principles of computer design now isn't it? assuming the soft core has built in routines to service requests for reset and during an exception. But a regular core like x86 or ARM seem to have fixed routines to serve exception faults like a divide-by-zero error etc whereas the soft core here seems to have a generic address to serve resets and exceptions. As you said, these routines could be stored on the on-chip memory, but didn't specify how or where.

3. Im following the SOPC VHDL tutorial downloaded from the altera FTP site. I have now been able to get a VHDL model of the system which I have instantiated in my top level design file but im running into compile time errors. Heres the code:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY lights IS
  PORT (
    SW       : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
    KEY      : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
    CLOCK_50 : IN  STD_LOGIC;
    LEDG     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    ); 
END lights;
ARCHITECTURE Structure OF lights IS
  COMPONENT nios_system
    PORT (
      clk                     : IN  STD_LOGIC;
      reset_n                 : IN  STD_LOGIC;
      out_port_from_the_LEDs  : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
      in_port_to_the_Switches : IN  STD_LOGIC_VECTOR (7 DOWNTO 0)
      ); 
  END COMPONENT;
  BEGIN 
  -- Instantiate the Nios II system entity generated by the SOPC Builder 
    
  nios_system_inst : nios_system
    port map(    
      out_port_from_the_LEDs => LEDG,
      clk => CLOCK_50,
      in_port_to_the_switches => SW,
      reset_n => KEY(0)
      );
END Structure;