Forum Discussion
Altera_Forum
Honored Contributor
18 years agoIt seems to me that problem has been fixed.
1. All `include directives should be REMoved and should serve as for memory reminder 2. All previously included files with instantiating modules should be directly added in current project via PROJECT main menu item. 3. Create component just with 'root' verilog file and other modules will be linked due to project setup. I just test it with SOPC builder v.7.0. Andrey