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Altera_Forum
Honored Contributor
17 years agoJust put a dual-clock FIFO in between them. This is how it's done throughout the Avalon ST based components. Use the rdempty signal on the read side to provide your valid signal. Use the wrfull signal on the write side (and maybe wrusedw depending on the ready latency) to provide the ready signal.
Can't get easier than that. Probably take you all of 10 minutes to code. Be sure to pass the startofpacket, and endofpacket and any other needed signals through the FIFO. Jake