some warning I don't understand

Question

hey,

I am new in Quartus so be patient:) ,I am buliding a simple a simple memory game,writing in VHDL,after comp' I recived some warning that I don't understand

1) warning: output pins are stuck at vcc or gnd

warning (13410): pin "sevensegment1[0]" is stuck at vcc

warning (13410): pin "sevensegment1[4]" is stuck at vcc

2) warning: found 27 output pins without output pin load capacitance assignment

info: pin "lightleds[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pf for timing analysis

3) warning: following 2 pins have nothing, gnd, or vcc driving datain port -- changes to this connectivity may change fitting results

info: pin sevensegment1[0] has vcc driving its datain port

info: pin sevensegment1[4] has vcc driving its datain port

4) warning: the reserve all unused pins setting has not been specified, and will default to 'as output driving ground'.

5) warning: found pins functioning as undefined clocks and/or memory enables

info: assuming node "clk" is an undefined clock

info: assuming node "sample" is an undefined clock

I will be very glad for some help

thx

altera_forum · Answer

1) Quartus has determined that your logic keeps those two pins always set at "1". If that is what you intended, then it's OK. If it's not, then you have a mistake in your logic design.

2) If you specify the load capacitante that's connected to each output pin, Quartus will be able to do a more acurate timming analysis.

You didn't specify it and Quartus it's telling you it's assuming a 0pF load (ideal). You problably don't have to worry about it.

3) Comes from point 1

4) Quartus is telling you what it's doing with the unused pins.

5) IIRC, it's because you haven't specified clock constraints for your "CLK" and "Sample" signals.

altera_forum · Answer

For 4) most dev-boards I worked with uses "As Input-Tristated" or same with week pull for configuration. You can select this in the device settings. You should look into the manual of your board, because when there are other components connected to the FPGA you are not using right now there is the possibility to shortcut things with "output to gnd". Input-Tristated is most times more safe for the components around, but must not be everytime like that.

altera_forum · Answer

thank you very much!

altera_forum · Answer

hey,

I have two more warning , I would like to some help

1) Warning: 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder

2) Warning (10230): Verilog HDL assignment warning at DecsionDevice.v(17): truncated value with size 32 to match size of target (5)

Tnx

altera_forum · Answer

1. I suggest you do as the kind folks say and check the reports folder.

2. Verilog literals (ie, 10) are 32 bit unless you specify otherwise. You probably have something like

reg [4:0] myReg;

...

myReg <= 10;

I also suggest you use Google.

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some warning I don't understand

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