some warning I don't understand

1) Quartus has determined that your logic keeps those two pins always set at "1". If that is what you intended, then it's OK. If it's not, then you have a mistake in your logic design.

2) If you specify the load capacitante that's connected to each output pin, Quartus will be able to do a more acurate timming analysis.

You didn't specify it and Quartus it's telling you it's assuming a 0pF load (ideal). You problably don't have to worry about it.

3) Comes from point 1

4) Quartus is telling you what it's doing with the unused pins.

5) IIRC, it's because you haven't specified clock constraints for your "CLK" and "Sample" signals.