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Altera_Forum's avatar
Altera_Forum
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15 years ago

some warning I don't understand

hey, I am new in Quartus so be patient:) ,I am buliding a simple a simple memory game,writing in VHDL,after comp' I recived some warning that I don't understand 1) warning: output pins are s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

1. I suggest you do as the kind folks say and check the reports folder.

2. Verilog literals (ie, 10) are 32 bit unless you specify otherwise. You probably have something like

reg [4:0] myReg;

...

myReg <= 10;

I also suggest you use Google.