some advice needed...

It is not really clear what kind of performance that you are refering to.

Are you refering to the study of the influence of e.g. max operation speed to external influences such as temperature, changes in supply voltage etc...

On silicon chips, the maximum operating speed is often evaluated by using ring oscillators. Here an odd number of invertors is put in cascade and fed back from output to input.

The loop delay time is than simply the inverse of the oscillation frequency.

The delay in a single invertor is determined by the loop delay time divided by the amount of invertors in the loop.

If you use enough invertors in the loop, you can get the oscillation frequency sufficiently low, such that you can measure it with other logic in the FPGA.

Making such a ring-oscillator should not be done in the usual way, as the whole chain would be optimized to a single inversion. You have to KEEP the original specified logic. You would also have to specifiy the placement and routing of individual invertors on the FPGA layout. This in order to control the interconnect delay.

What about some kind of brute force operation ?

implement a shift register with a length of all registers you have and connect the output of the shift register with it's input.

the content you shift is an alternating 1010101010... stream, so all registers must toogle.

also connect all available IOs to such bits of the register. maybe let some of the bit go through embedded multiplier and let these output be connected to your io pins to get more stress

this of course means you will have the maximum core and io current. and so so will need a very well designed power supply and themal cooling of your device.

i knew that other fpga companies like the one with an X in its name forbits such testings but i knew about a design where this works very well. (and the pcb from the manufacture of the device does not work) if your pcb is not very well done then this will unsolder your fpga and damage it of course. (as with the desing kit from that manufacfure)

but this is maximum stress and shows extremly what can be done when it is done perfectly.

first , thanks for your reply .

I understand what you mean.

I just needed some ideas how take the device to its limit.

the FPGA has built-in multipliers, memory etc. and I want to use them also in order get more information. my instructor gave us the idea to create pyramid of inverters , so we can check multiple outputs , how do you think such a structure will compile?

another advice I want to ask is about the most convenient and fast way

to program the fpga. I know VHDL , but I just wonder if there is some other and more convenient way since we don't need to create complicated design . ( i mean is there any exiting blocks that we can just attach together ??) .

thanks. :)

i think the hdl is a very simple solution for that.

this is a 1024 bit shift register loop in verilog hdl

reg [1023:0] myShiftBigReg;

always @ ( posedge clk )

myShiftBigReg <= { myShiftBigReg[1022:0] : myShiftBigReg[1023] };

if you need some embedded multipliers then you cann add somethink like that

reg [35:0] MyMulReg001;

always @ ( posedge clk )

MyMulReg001 <= myShiftBigReg[17:0] * myShiftBigReg[17:0];

this would add 1 multiplier 18x18

reg [71:0] MyMulReg002;

always @ ( posedge clk )

MyMulReg002<= MyMulReg001 * MyMulReg001 ;

this would add 2 multiplier 18x18

of course you could feed some bits into embedded memory cell as the address so the address is changing with every clock ...

you can stream the output of these memories into multipliers ...

this is very easily done in hdl i guess ...